Tesla has a new name for its silicon, a new number for its ambitions, and — most surprisingly — a second life for the supercomputer it killed last year. Tesla disclosed a revamped accelerator roadmap this week, according to AlexTech, in which its AI4, AI5, and AI6 chips become SI4, SI5, and SI6. SI stands for "super intelligence."
The rename is the least technical part of the story and the most telling. "Super intelligence" is the term the Trump administration ordered federal agencies to use in place of "artificial intelligence" in a September executive order, and Musk has already adopted it across his companies: SpaceXAI became SpaceXSI, Tesla AI became Tesla SI, and Tesla's owner's manuals now call the in-car computer the "SI Computer" instead of the FSD Computer, as Not a Tesla App spotted last month. The Justice Department launched its own Super Intelligence Task Force this week, according to The Register. In the span of a month, "AI" has become a word the industry's biggest names are quietly retiring — at least on the letterhead.
The headline number is SI6. Tesla estimates its sixth-generation inference chip will deliver 80 times the compute of the current AI4 (HW4) and nine times the memory — somewhere between 17,280 and 46,080 TOPS — when it arrives in 2029 or 2030. Treat that as a directional promise, not a spec sheet: Tesla doesn't disclose AI4's absolute compute, and it hasn't said which data formats SI6's numbers assume. For scale, Nvidia's Rubin is already shipping at 50 NVFP4 PFLOPS of inference performance.
The more concrete news is Dojo. The training accelerator Tesla disbanded in August 2025 — then restarted in January — returns as D3, and it abandons the thing that made Dojo distinctive: the SRAM-centric, wafer-scale design of the D1 and D2 chips. D3 is a multi-chiplet design using 2.5D and 3D packaging with stacked high-bandwidth memory — the same architecture the rest of the accelerator industry has converged on. Tesla disclosed no compute, memory, process, or schedule for D3, saying only that it will be optimized for "space, training and scaling," with versions possibly hardened for extraterrestrial deployment.
That last detail is pure Musk, but the architecture shift is pragmatic. Dojo's original bet was that a bespoke wafer-scale mesh could outrun the industry; the new bet is that chiplets and HBM — the mainstream stack — can scale further, faster. It's also a unification play: AI5, which taped out in April and is now in trial production at Samsung's Texas fab, is designed to handle both inference and training, and Musk is aiming for a new chip design every nine months.
What to watch: whether SI5 ships in volume in 2027 as planned, and whether D3 ever gets real numbers attached. The 80x figure is a 2030 promise; the test of this roadmap is the silicon that ships next.
— via AlexTech